Current metal patterning methods, including reactive ion etching (RIE) and damascene techniques, use anisotropic etching processes that make it possible to produce patterns having features with dimensions on the order of sub-half micron in size. In practice, such anisotropic etching results in the development of sharp corners (i.e., when viewed through the cross-section of the metal layer).
For example, FIGS. 1A and 1B schematically illustrate integrated circuits 1, 2 which have been produced using an RIE process (FIG. 1A) and a damascene process (FIG. 1B), respectively. In each case, desired metallized features 3 (e.g., conductor lines formed of aluminum) are shown associated with a suitable substrate 4 (e.g., formed of SiO.sub.2). For the RIE-prepared integrated circuit 1 of FIG. 1A, an outer layer 5 (e.g., including Si.sub.3 N.sub.4 and SiO.sub.2) is applied over the features 3 and the substrate 4. For the damascene-prepared integrated circuit 2 of FIG. 1B, the metallized features 3 are received within trenches 6 formed in the substrate 4.
In practice, such processing results in sharp corners 7', 7" (seen through the cross-section of the metallized features 3), respectively, along the tops 8 and at the bottoms 9 of the metallized features 3. The sharp corners 7', 7" tend to cause high stresses in the surrounding dielectrics. These high stresses have been found to cause cracks in the final passivation layer. S. Lee & K. Lee, "The Optimization of Passivation Layout Structure for Reliability Improvement of Memory Devices," Jpn. J. Appl. Phys., Vol. 35, Part 1, No. 10, pp. 5462-65 (Oct. 1996). These high stresses have also been found to cause "cratering" in the fuses which have come to be formed on integrated circuits for various purposes, when such fuses are laser-blown.
In an effort to reduce stress-induced cracking, Lee et al. suggest increasing the passivation thickness. The authors recognize, however, that the beneficial effects of this suggestion are limited by a corresponding increase in the brittleness of a thicker layer. U.S. Pat. Nos. 5,416,048; 4,425,183; and 4,352,724 each suggest rounding of the top corners 7' to achieve various improvements in the etching of semiconductors. For U.S. Pat. Nos. 5,416,048 and 4,425,183, and as is further disclosed in U.S. Pat. No. 4,780,429, the etched metallized features 3 can further be provided with sloping sides to achieve various other improvements. The sloping sides resulting from such manufacturing processes are formed, however, using the oxides of the metals which form the metallized features 3. Such formation has been found to yield moderately high leakage currents and, at times, to extend across the gap which must be preserved between the adjacent metallized features 3 (e.g., adjacent metal vias or lines).
Therefore, the primary object of the present invention is to reduce deleterious effects, such as cracking of the final passivation layer or "cratering" of the fuse layer of a manufactured integrated circuit, by reducing the high stresses which can be developed in the dielectrics which surround the features being formed on the integrated circuit. Another object of the present invention is to accomplish this in a way which is fully compatible with conventional metal patterning methods, including RIE and damascene techniques.